The manufacture of semiconductor devices is primarily accomplished with photolithographic techniques. During the manufacturing process, multiple layers of a circuit pattern are built up on a semiconductor wafer. This is accomplished by projecting an image on a mask or reticle containing the circuit pattern onto a wafer coated with a photosensitive resist. Feature sizes imaged onto the semiconductor wafer are typically in the range of 0.5 microns or smaller. Due to the extremely small feature sizes and the requirement to expose multiple layers as part of the manufacturing process, the use of an alignment system to align the mask image on the semiconductor wafer is required. Often, the alignment accuracies necessary are in the range of 0.1 microns or less. One such alignment system is disclosed in U.S. Pat. No. 4,697,087 entitled "Reverse Dark Field Alignment System For Scanning Lithographic Aligner" issued to Frederick Y. Yu on Sep. 29, 1987, which is herein incorporated by reference. Therein disclosed is an alignment system wherein a wafer having a wafer target thereon, and a mask having a mask target thereon, are aligned with respect to each other. In the manufacture of semiconductor wafers, processing variables such as wafer characteristics, number, thickness, and type of surface layers, often makes alignment difficult. The variation in an alignment signal is a function of these processing variables and is referred to as process sensitivity. This process sensitivity often complicates the ability of an alignment system to accurately obtain the position of alignment marks placed on a wafer. Therefore, there is a need for an alignment system that is relatively process insensitive or that can obtain accurate positioning information irrespective of process variations.